Skip to content

Merge upstream llvm into amd-debug - #4171

Merged
mariusz-sikora-at-amd merged 531 commits into
amd-debugfrom
amd/dev/masikora/amd-debug-merge-candidate
Aug 28, 2026
Merged

Merge upstream llvm into amd-debug#4171
mariusz-sikora-at-amd merged 531 commits into
amd-debugfrom
amd/dev/masikora/amd-debug-merge-candidate

Conversation

@mariusz-sikora-at-amd

Copy link
Copy Markdown

Merge up-to upstream.

[1]

commit 3fa8cf1d042015585db89f60a345acac0d068835 (HEAD -> amd/dev/masikora/amd-debug-merge-candidate)
Merge: 786c25ed6f80 23fa5a85bc1b
Author: Mariusz Sikora <mariusz.sikora@amd.com>
Date:   Fri Aug 28 02:31:11 2026 -0400

    Merge llvm/main into amd-debug

diff --git a/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip b/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip
index f5381dcfbb3f..bda8df61b33c 100644
--- a/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip
+++ b/clang/test/CodeGenHIP/debug-info-amdgcn-abi-heterogeneous-dwarf.hip
@@ -214,7 +214,7 @@ __device__ void Test_Func_StructTrivialCopyNoMove(StructTrivialCopyNoMove) {}
 //
 __global__ void Test_Kern_StructTrivialCopyNoMove(StructTrivialCopyNoMove) {}
 // CHECK-LABEL: define dso_local void @_Z28Test_Func_StructNoCopyNoMove18StructNoCopyNoMove(
-// CHECK-SAME: ptr addrspace(5) nofree noundef align 1 dead_on_return dereferenceable(1) [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG143:![0-9]+]] {
+// CHECK-SAME: ptr addrspace(5) nofreeobj noundef align 1 dead_on_return dereferenceable(1) [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG143:![0-9]+]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
 // CHECK-NEXT:    [[DOTINDIRECT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
 // CHECK-NEXT:    store ptr addrspace(5) [[TMP0]], ptr addrspace(5) [[DOTINDIRECT_ADDR]], align 8

[2]

commit def62acdf9019b952b6776a260565237d6311bb6 (HEAD -> amd/dev/masikora/amd-debug-merge-candidate)
Merge: 3fa8cf1d0420 86779ac9575c
Author: Mariusz Sikora <mariusz.sikora@amd.com>
Date:   Fri Aug 28 03:04:52 2026 -0400

    Merge llvm/main into amd-debug

diff --git a/llvm/unittests/IR/MetadataTest.cpp b/llvm/unittests/IR/MetadataTest.cpp
index 2c6537e886ad..36800e2d03b5 100644
--- a/llvm/unittests/IR/MetadataTest.cpp
+++ b/llvm/unittests/IR/MetadataTest.cpp
@@ -5233,7 +5233,8 @@ TEST_F(DIPropertyTest, get) {
   auto GetMember = [&](StringRef Name) {
     return DIDerivedType::getDistinct(
         Context, dwarf::DW_TAG_member, Name, nullptr, 0, nullptr,
-        getBasicType("basictype"), 8, 8, 0, std::nullopt, {}, DINode::FlagZero);
+        getBasicType("basictype"), 8, 8, 0, std::nullopt,
+        dwarf::DW_MSPACE_LLVM_none, {}, DINode::FlagZero);
   };

   StringRef Name = "x";

adams381 and others added 30 commits August 26, 2026 09:28
These four CIR tests now compile and check clean with x86_64
calling-convention lowering on, unblocked by the packed-record (llvm#218505)
and vptr-record (llvm#218457) work. Stripping the flag moved zero CHECK
lines: the output the pass produces for these four is exactly what was
already pinned.

Assisted-by: Cursor / claude-opus-5
This provides missing components required to run LLVM libc hermetic
tests, for example, with QEMU:
- Redirect of output, time and exit to semihosting.
- Linker script.
- Extra LIBC_MATH_ASSUME_ROUND_NEAREST_ONLY setting for
LIBC_CONF_MATH_OPTIMIZATIONS to make hardfp tests pass.
…bool_t. (llvm#218667)

This makes the casting behaviour more explicit:
> to/from_svbool  : lane-count changing casts
> to/from_svcount : reinterpretation casts
…218777)

Enable DAGTypeLegalizer::ModifyToType to widen scalable vectors whose
element counts are not integer multiples. Split the source and
destination into their largest common scalable subvector type, extract
the source parts, append poison or zero fill parts, and concatenate
them.
…attribute APIs (llvm#218901)

Use discardable attribute APIs and typed operation accessors throughout
the OpenACC and OpenMP dialects, conversions, translation, utilities,
and tests.

Keep ComputeRegionOp inherent properties in the property dictionary and
discardable attributes in the attribute dictionary.

Assisted-by: Codex
Notify pattern rewrite listeners while replacing the operands of both
write-like users after accumulator shuffling.

Add focused coverage that does not depend on the separate accumulator
rewrite.

Assisted-by: Codex
This PR optimizes the AArch64 backend for 128-bit integer squaring
(`u128 x * x`).

It updates the instruction selection logic to combine `(A + B) + B` into
`A + (B << 1)`. This allows the compiler to emit a single, optimal `add
... lsl #1` instruction instead of multiple separate `add` instructions.

A baseline test was added in the first commit, and the optimization is
provided in the second commit to clearly highlight the codegen
improvements.

Fixes llvm#213775
…ifiers (llvm#217665)

MergeFunctions currently merges functions with identical bodies even
when
their function-level !kcfi_type metadata contains different type
identifiers.

This can redirect calls or function pointers to a function with a
mismatched
KCFI type identifier, potentially causing KCFI checks to fail at
runtime.

Compare function-level !kcfi_type metadata in FunctionComparator so that
functions with different KCFI type identifiers are not merged.

Add a minimal regression test covering two identical functions with
different
KCFI type identifiers.

Fixes llvm#217629
There is no CHECK prefix; remove and regenerate with X32/X86 check
lines.

As suggested in llvm#217378.
Use typed operation accessors and explicit discardable attribute APIs in
the Tosa dialect, conversions, target handling, and validation.

Assisted-by: Codex
…vm#218575)

An importing compile unit emits its own DW_TAG_module skeleton, and that
skeleton can name a different DW_AT_LLVM_include_path than the unit
built from the .pcm. For example, a Swift unit names the .swiftmodule
while the companion Clang module names the framework bundle.

The classic linker gets this from DeclContext uniquing. f03b9d7
made the parallel linker's type pool pick the right copy, but the type
pool only covers ODR languages. This addresses the non-ODR case.

Add a link-global ModulePool, using the dotted module path as the key. A
module unit records where it put each DW_TAG_module, either as a type
entry or as a section + offset. Because the import may not exist during
cloning, we emit a placeholder and only emit it when the anchor is fully
resolved.

A .pcm holds the description of the module it was built for, and also a
partial copy of every module that it imports. Only the first is the
canonical description, so a unit only claims itself as the target for
that module, and not for the ones it imports.

The same module can also be built more than once, with different compile
flags. Every .pcm gets a unit, so two units can describe the same
module. To make this deterministic, the one that came earlier in the
link wins, which matches what we do for identical types.

An importer whose own copy already sits in the type pool needs none of
this, because the pool has already uniqued it.

rdar://185156929

Assisted-by: Claude
This patch removes forward declarations of classes and structs that
are no longer referenced anywhere in MLIR.
…7263)

This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions

It continues the work started in llvm#190961, llvm#193273, llvm#199990, llvm#209252,
, llvm#211609,  llvm#216757 and llvm#217017.

This PR implements the conversions for the following:
1) "int to float" intrinsics:
   * vcvt_f32_s32
   * vcvtq_f32_s32
   * vcvt_f32_u32
   * vcvtq_f32_u32
   * vcvts_f32_s32
   * vcvts_f32_u32
   * vcvt_f64_s64
   * vcvtq_f64_s64
   * vcvt_f64_u64
   * vcvtq_f64_u64
   * vcvtd_f64_s64
   * vcvtd_f64_u64

2) "float width conversion" intrnsics:
   * vcvt_f16_f32
   * vcvt_high_f16_f32
   * vcvt_f32_f64
   * vcvt_high_f32_f64
   * vcvt_f32_f16
   * vcvt_high_f32_f16
   * vcvt_f64_f32
   * vcvt_high_f64_f32
   * vcvtx_f32_f64
   * vcvtxd_f32_f64
   * vcvtx_high_f32_f64

The corresponding tests are moved from:
  * clang/test/CodeGen/AArch64/

to:
  * clang/test/CodeGen/AArch64/neon/

The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
…#218735)

Relands llvm#217870 with a fix for the failure in `clang/test/Interpreter/emit-llvm.cpp` seen on ppc64le
…#218964)

Reverts llvm#215152

This change breaks -Wl,-z,execstack for target offload.
…218931)

These 8 CIR tests compile clean with x86_64 calling-convention lowering
on, but their CHECK lines still pinned the pre-coercion CIR: raw record
types in signatures, plain by-value loads for temporaries with a
non-trivial destructor, and matching store/load pairs for empty records.
The pass now emits the ABI-correct shape instead: sret return
parameters, a dropped or byref-marked argument for records that carry no
data or that need pass-by-reference, and a `#cir.poison` placeholder
where a value the pass ignores used to be stored.

Assisted-by: Cursor / claude-opus-5
…tinations. (llvm#217436)

Allow call slot optimization for non-dereferenceable destinations when
execution is guaranteed to reach the store. For this, check if the call
has both willreturn and nounwind attributes, and there are no
instructions between the call and the store that might trap or throw.
Since the store would trap anyway if the destination pointer was not
dereferenceable, we can forward the pointer to the call.
…vm#216758)

Currently, after a load instruction resulting in a half-vector tuple,
LLVM emits an extra fmov for explicitly zeroing the upper-half of the
vector register when returning a value in the tuple as the full 128 bit
vector.
This is unneeded as the load instruction already zeros the upper half of
the registers in the tuple.

Add special case to existing peephole function that can recognize the D
sub-reg tuple defining opcode and allow removing the extra FMOV

Full List of Load Instructions Tested:
LD1Twov: 8b, 4h, 2s, 1d
LD1Twov_POST: 8b, 4h, 2s, 1d
LD1Threev: 8b, 4h, 2s, 1d
LD1Threev_POST: 8b, 4h, 2s, 1d
LD1Fourv: 8b, 4h, 2s, 1d
LD1Fourv_POST: 8b, 4h, 2s, 1d
LD2Twov: 8b, 4h, 2s
LD2Twov_POST: 8b, 4h, 2s
LD3Threev: 8b, 4h, 2s
LD3Threev_POST: 8b, 4h, 2s
LD4Fourv: 8b, 4h, 2s
LD4Fourv_POST: 8b, 4h, 2s
…m#218951)

With llvm#218872, some code generated by `tblgen` containing `getContext()`
now uses `OpTyp::getContext()` if that op has a `context` property
instead of the intendend `Operation::getContext()`. This PR qualifies
the access such that the intended function is always called.

Signed-off-by: Ingo Müller <ingomueller@google.com>
…vm#218810)

There is currently a bug in the path on ARM64 Windows, so this step
always fails. Running it after a successful build doesn't make much
sense anyway since since we don't need to see the logs for a good build.
Also, we risk having it fail the whole job even after a successful build
(like what is currently happening on ARM64 Windows), so that's another
reason only to run this when the bulid fails.
…lvm#218345)

Use the destination LLT kind when selecting the scalar type used to
lower G_EXTRACT. Any-scalar destinations continue using sN, while
specific integer or pointer destinations use iN.

Gap uncovered when adding CSE support for GISel Post-Legalizer combiner.
llvm#217258

Assisted-by: Codex
---------

Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha@gmail.com>
Summary:
This was done for every executable that was loaded. In the current
OpenMP use this never caused issues, but we need to check if this was
already done so we don't leak the memory.
…unified (llvm#218976)

Example:
```fortran
subroutine foo(n)
   integer, intent(in) :: n
   real :: tmp(n)
```

Compiled with -gpu=mem:unified -fstack-arrays, tmp still ends up in
malloc_unified: CudaHeapAllocPromotion marks the allocation
fir.must_be_heap, which StackArrays then skips, so -fstack-arrays is
silently dropped. Under mem:unified the stack is device accessible, so
the promotion is a placement choice there. Under mem:managed only the
managed allocator is, so it stays a correctness requirement.

Fix: add a stack-arrays option to the pass and skip the promotion when
it is set and the mode is unified.
…lvm#215883)

Since we #error immediately before, a comment is needed to explain the
purpose of the define.
…P_LLVM_user (llvm#216314)

DW_OP_LLVM_NVIDIA_mux takes an LEB128 selector, giving NVIDIA an
extension space behind a single opcode in the DW_OP_LLVM_user space. The
selector is opaque to LLVM; no NVIDIA operation semantics are defined
here. This mux opcode is a subop of DW_OP_LLVM_user.

Assissted-by: LLM
…#218988)

This makes it possible to manually build the Windows binaries for
releases.
aeubanks and others added 12 commits August 27, 2026 19:03
…sections (llvm#219289)

Or else we miss flags like SHF_X86_64_LARGE.
ASTContext::getASTRecordLayout used a fixed 1ULL << 60 threshold for
err_struct_too_large, regardless of the target's size_t width.

Scale the threshold to the target's size_t width instead, so it is below
(1 << 32) on 32-bit architectures. Diagnosing the overflow in Sema
avoids the crash in codegen.

rdar://183351516
[flang] Speed up large CHARACTER DATA initializers

Repeated CHARACTER(KIND=1) array constants were lowered as one
fir.insert_value per element. Converting those chains to LLVM IR is
quadratic and can make compilation take tens of minutes.

Lower consecutive equal KIND=1 character elements with
fir.insert_on_range
and emit full-range initializers as a single flattened [N x i8] LLVM
global
string, keeping Fortran blank padding.

A 160000-element character DATA statement now compiles in well under a
second and before was more than 10 minutes.
This patch removes the unused IDHash parameter from several functions.
Now that FoldingSetTrait<SDVTListNode>::Equals no longer checks IDHash,
no implementation of Equals uses this parameter.

Assisted-by: Antigravity
…ts (part 2) (llvm#219286)

llvm#218753 broke LLVM CI because
it added a new test in `ScalarizeMaskedMemIntrin` that was not opted out
of during profcheck. Profcheck failed because this pass creates new
branches that did not attach branch weight metadata. We don't have any
information on the distribution of masks at runtime, so we have to mark
branch weights as explicitly unknown.

This basically extends llvm#181568,
Aiden am I missing something for why you didn't add the branch weight
metadata for all branch creation before?

Tested the `ScalarizeMaskedMemIntrin` tests with profcheck locally and
they all pass.
This adds support for the OpenMP 5.2 extension sentinels: !$omx, c$omx,
*$omx in fixed form and !$ompx in free form. Known directives after
these sentinels are handled just like !$omp, and unknown ones are
ignored with a warning so code using vendor extensions stays portable.
Added lit tests covering fixed form, free form, and the
ignore-with-warning behavior.

Assisted-by: Claude Opus 4.6

---------

Co-authored-by: Chandra Ghale <ghale@pe34genoa.hpc.amslabs.hpecorp.net>
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek@amd.com>
…er (llvm#219346)

This patch initializes NextBundleInfo at the top of ReadHeader to
prevent an uninitialized iterator comparison.

ReadHeader has several early return points where it exits without
reading any bundles.  Upon an early return, NextBundleInfo never reaches
the assignment at the bottom of ReadHeader:

  NextBundleInfo = BundlesInfo.begin();

leaving NextBundleInfo default-constructed.  A subsequent call to
ReadBundleStart then attempts an invalid iterator comparison:

  if (NextBundleInfo == BundlesInfo.end())

where NextBundleInfo is still default-constructed.

This bug was discovered with tightened epoch checks in
StringMapIterBase.

Assisted-by: Antigravity
…sult`. (llvm#214501)

Implicit integer promotions make it a bit difficult to deduce the
correct type in the following expression:
```
std::uint64_t calc_array_size(std::uint16_t width, std::uint16_t height) {
    return width * height;
}
```

Originally, Clang-Tidy suggested to use the following code:
```
return static_cast<long long>(width) * height;
```

It is fully correct according to the C++ rules, but it makes it a bit
harder to reason for people. This change adds a more readable "FixIt"
taking into account the source type and avoid intermediate
representations.

Co-authored-by: Dmitrii Kuragin <dkuragin@adobe.com>
@rocm-cciapp

rocm-cciapp Bot commented Aug 28, 2026

Copy link
Copy Markdown

@dstutt dstutt left a comment

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

Not conflict, but fixes?

@mariusz-sikora-at-amd

Copy link
Copy Markdown
Author

LGTM

Not conflict, but fixes?

Yes, no conflicts, just update for new tests.

@mariusz-sikora-at-amd
mariusz-sikora-at-amd merged commit ff0368f into amd-debug Aug 28, 2026
32 of 34 checks passed
@mariusz-sikora-at-amd
mariusz-sikora-at-amd deleted the amd/dev/masikora/amd-debug-merge-candidate branch August 28, 2026 08:21
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.